System-Level QEMU Co-Simulation

  • Level up and perform full System HW-SW verification at pre-silicon level
    • Iterate HW and SW changes 10X faster at RTL compared to FPGA or system prototypes
    • Begin HW-SW integration much sooner in development process
  • Virtual machine to VIP co-sim/co-emulate environment extends existing SV/UVM testbench + VIPs
  • X86 Host
    • Supports PCIe/CXL root complex VIP
    • Run Linux kernel drivers, compliance and benchmarking programs, and application software
  • Arm, RISC-V embedded systems
    • Supports AMBA (AXI/AHB/APB) VIP
    • Run bare metal code or RTOS embedded systems
  • Run OS and SW unmodified from actual system configuration
  • Debug trace shows QEMU to remote PCIe/CXL/AXI ports transactions
  • Avery's implementation of QEMU co-simulation is optimized for fastest performance including KVM mode and iWARP technology
  • Simulations are scalable to 10s to 100s of instances for regression over OS versions and HW configurations

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NVMe SSD controller benchmark Boot Linux and run real workloads like FIO performance benchmarking application

Use with SimAccel for 100X speed-up or more!

Actual HW
(sec)
Simulation
(sec)
SimAccel
(sec)
SimAccel
Speedup
Linux Boot201140402850%
FIO11152010011520%
FIO (Random WR+RD, BS=4K, IO_DEPTH=64, DATA=4M)

QEMU Co-Sim Use Model for verifying CXL 2.0 Type 3 Design

  1. Run simulator with CXL RP VIP + DUT RTL
  2. Run QEMU w/ CXL Linux 5.12.rc2 and connect to simulation
  3. SSH into QEMU VM run linux commands and programs such as lspci –v to find RTL DUT device

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