Avery Design Verification IP

Management Team

Avery management are committed to delivering the highest quality products and expert technical support.

Chilai Huang, President/CEO. Mr. Huang got his Ph. D. in 1982. He has been working on the EDA business since then. He was the co-founder with Dr. Prabhu Goel of Gateway Design Automation, Inc. He and Mr. Phil Moorby worked on the language definition and first implementation of Verilog. Since then, he has been working in fault simulation, timing verification, and synthesis areas. He was responsible for Cadence’s RTL synthesis effort for several years and eventually led the whole synthesis project. He left Cadence and started Avery at 1998.

Chris Browy, Sr Vice President of WW Sales/Marketing. From 1989 to 1998, Mr. Browy held various positions at Cadence Design Systems including Director of ASIC Design Services, Director of Top-down IC Design Practice, and marketing manager for synthesis, timing analysis, and test products. Prior to 1989, Mr. Browy held numerous other positions in applications engineering and hardware systems development. Mr. Browy has been responsible for system and ASIC design projects involving large-scale ATM switching systems, Non-linear digital video editing systems, and massively parallel multiprocessors. Mr. Browy received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984.

Andy Stein, Vice President of North America Sales.  Mr. Stein has had more than 25 years of sales management experience in the EDA industry and helped several startup companies pioneer their products and reach their financial goals, which often led to acquisition by companies such as Cadence Design Systems and Synopsys. These startups include such companies as Gateway Design Automation, Viewlogic Systems, Co-design Automation, Nextop Software , Jasper Design Automation and now Avery Design Systems.
Mr. Stein started as an IC design engineer for TRW after completing both an M.S.E.E and B.S.E.E, graduating in the top 1% of his class from the University of Illinois in 1986.

Zhihong Zeng, Verification IP Architect. Mr. Zeng received his PHD in semi-formal based functional verification at UMASS, Amherst. Prior to his PHD, he earned M.S.E.E on ASIC designer and started a career as an IC designer in Lenovo. Since joined the force in Avery, Mr. Zeng architected and led development in various verifications IPs like, USB, MIPI/Unipro, SOP/PQI, NVMe and PCIe and oversees R&D of other VIPs.

Kai-hui Chang, EDA Tool Architect. Mr. Chang joined Avery in 1999. He co-developed Avery’s early tools for functional verification and was  responsible for Avery’s parallel logic simulator, SimCluster. After receiving his PhD in CSE from the University of Michigan in 2007, he  rejoined Avery and codeveloped and architected Avery’s formal and semi-formal tools including Property Synthesis, SimXACT and Retention/Reset Optimization.  Mr. Chang published 30+ papers and holds several patents from his work
both in the academia and the industry.