Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express
Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking about DPU architecture for…
PCI Express VIP from Avery Design Systems Selected by Fungible for Ensuring Compliance, Connectivity in Hyperscale Data Centers
Tewksbury, MA., Feb 28, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, to ensure compliance and connectivity of its Fungible Data Processing Unit™ (DPU). The Fungible DPU™ is an industry-first and addresses the most…
AI expands HBM footprint
High bandwidth memory (HBM) is becoming more mainstream. With the latest iteration’s specifications approved, vendors in the ecosystem are gearing to make sure it can be implemented so customers can begin to design, test and deploy systems. Avery Design Systems has built a verification platform based on its own tested verification IP (VIP) portfolio to…
Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard
Rambus uses Avery HBM3 memory model to verify its HB
Avery Design Partners with S2C to Bring PCIe® 6.0 and LPDDR5 and HBM3 Speed Adapters to FPGA prototyping solutions for Data Center and AI/ML SoC Validation
Avery Design Systems, a leader in functional verification solutions, today announced the latest in native FPGA speed adapters for PCIe® Gen6 and advanced memory technologies for LPDDR5 and HBM3
Pre-Silicon Verification – The Newest Approach to Accelerating Time-to-Market of Advanced Computing Capabilities
Chris Browy, Vice President of Worldwide Sales and Marketing of Avery Design Systems, is a go-to expert on all things functional verification. Avery, a well-established provider of functional verification solutions, has been around since 1998 supporting a growing and complementary line of SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for…
CAST and Avery Design Systems expand IP partnership to support next generation high-bandwidth automotive networking and control systems
Integrated IP/VIP solutions for CAN XL and TSN Ethernet enable rapid design, verification and deployment of SoCs for new protocols Tewksbury, MA. and Woodcliff Lake, NJ. – July 27, 2021 – Avery Design Systems, a leader in functional verification solutions, and semiconductor intellectual property supplier CAST, Inc., announced today they have expanded their partnership to…