Avery Announces 800G Ethernet VIP virtual network co-simulation platform, enabling SoC pre-silicon validation in real networked application environments
Fully tested VIP can be leveraged in virtual networking scenarios and across all network stack layers and protocols, accelerating verification closure SANTA CLARA, CA At the Flash Memory Summit (#FMS2022) – August 2, 2022 – Avery Design Systems today announced that its fully-tested Verification IP (VIP) for 800Gbps Ethernet can now be used to perform virtual…
Mobiveil and Avery Design Systems extend partnership to accelerate design and verification of NVMe 2.0-enabled SSD development
MILPITAS, CALIF. –– August 2, 2022 –– Mobiveil, Inc and Avery Design Systems today announced an expanded partnership to help customers accelerate NVMe based SSD design and verification. The complementary IP/VIP solution combines Mobiveil’s design IP for NVM Express, DDR4 and LDPC IPs with Avery’s verification IPs for NVMe, DDR4 and ONFI and NVMe virtual…
Avery Design Announces CXL™ 3.0 VIP
Support for increased bandwidth and latest features in newest version of standard provides developers with an efficient pre-silicon validation methodology Tewksbury, MA., August 2, 2022 — Avery Design Systems, the leader in functional verification solutions, today announced availability of CXL 3.0 VIP. Computer Express LinkTM (CXL) is an open industry-standard interconnect offering coherency and memory…
Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
TenaFe Relies on Avery VIP for its PCIe Gen4 NVME DRAMless SSD controller targeting next-generation 5G and IoT applications Santa Clara, CAAugust 1, 2022 — at the Flash Memory Summit, Avery Design Systems, a leader in functional verification solutions, today announced its NVMe®, PCIe® and AXI® Verification IP (VIP) has been adopted by TenaFe, to…
Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity
Tewksbury, MA., June 21, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications. eTopus designs ultra-high speed mixed-signal semiconductor solutions for high-performance…
Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
Avery to offer VIP, verification aids to enable design with recently-announced die-to-die interface standard backed by industry leaders Tewksbury, MA – June 15, 2022 – Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage…
Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express
Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking about DPU architecture for…