News

CAST and Avery Design Systems expand IP partnership to support next generation high-bandwidth automotive networking and control systems

Integrated IP/VIP solutions for CAN XL and TSN Ethernet enable rapid design, verification and deployment of SoCs for new protocols Tewksbury, MA. and Woodcliff Lake, NJ. – July 27, 2021 – Avery Design Systems, a leader in functional verification solutions, and semiconductor intellectual property supplier CAST, Inc., announced today they have expanded their partnership to…

Avery Levels Up, Starting with CXL

Article Posted to SemiWiki by Bernard Murphy on 05-25-2021 at 6:00 am. Read the source article here Let me acknowledge up front that Avery isn’t the most visible EDA company around. If you know of them, you probably know their X-propagation simulator. Widely respected and used, satisfying a specialized need. They have also been quietly…

Avery Design Launches PCI Express 6.0 Verification IP to Enable Early Development, Compliance Checking for New Version of Standard

Tewksbury, MA – May 25, 2021 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of major updates to the company’s flagship PCI Express® (PCIe®) 6.0 and PIPE 6.0 VIP solution. Avery unveiled the solution at the PCI-Sig DevCon event this week. The solution supports the latest features and…

Avery Design Systems and Rambus Extend Memory Model and PCIe® VIP Collaboration

Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory…

Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systemsAvery PCIe and CXL Verification IP enabled Astera Labs to get to market faster Tewksbury, MA., April 28, 2021 Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions…

Avery Design Debuts CXL™ 2.0 System-level VIP Simulation Solution

Tewksbury, MA., April 15, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced its CXLTM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL…