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Siemens announces acquisition of Avery Design Systemsclick here for more information

Robust SystemVerilog / UVM Verification IP Portfolio

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Virtual host/embedded QEMU and VIP/RTL system co-simulation

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Semi-Formal applications for X-verification

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Parallel simulation acceleration and FPGA acceleration

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FPGA prototyping solutions and prototyping IPs

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Verification Productivity Solutions

What’s New

Siemens expands industry-leading integrated circuit verification portfolio with acquisition of Avery Design Systems
Siemens Digital Industries Software today announced that it has signed an agreement to acquire Avery Design Systems, Inc., the leading simulation-independent verification IP supplier.
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Events

December 6-7, 2022 – Avery will be exhibiting at DV Con Europe in Munich. Visits us in Booth 502.

January 24 -26, 2023Chiplets Summit San Jose

Feb 27 – March 3, 2023 – DVCon US San Jose

June 13-15, 2023PCI-SIG Developers Conference San Jose

Industry’s Largest Portfolio Of Verification IP

  • 60+ standard protocols
  • 5+ industry exclusive VIPs
  • 20+ compliance test suites
  • 10+ IP partnerships
  • 10+ year track record
  • 7 of the top 12 NVMe SSD controllers
  • Flexible licensing
    • Protocol-specific
    • VIP Portfolio

Avery’s PCIe 6.0 Verification IP

Overview and code demo of Avery’s flagship PCIe® VIP supporting the latest PCIe® 6.0 specification,

Broadest Set Of IP Partnerships In The Industry

What Our Clients Are Saying

Avery’s CXL virtual platform and VIP co-simulation solution helped reduce our validation time as we were able to perform extensive pre-silicon verification on our Leo Memory Connectivity Platform that supports CXL 2.0 and 1.1 technologies, and we are ready for real-world deployment. We look forward to utilizing a similar approach as we evolve next generation CXL designs

Suresh Sankaralingam, head of DV and Emulation, Astera Labs

We use Avery’s HBM-Xactor and DDR-Xactor VIP as a key part of our Memory Controller verification enabling us to comprehensively verify our Memory Controller Cores. We have found the memory models and associated support to be very high quality and recommend Avery’s VIP to all our customers for robust SoC verification

Brian Daellenbach, Senior Director Rambus Controller Group

We have been pleased to collaborate with Avery Design to support the validation of our XpressRICH3 IP using Avery testbench and compliance tests on behalf of our mutual customers. We are now pre-qualified with Avery VIP and have enhanced the quality of our IP in the process which is important for customers seeking the proven, interoperable solutions.

Stephane Hauradou, CTO of PLDA

We are excited to work with Avery to help automotive engineers develop safer systems quicker through the industry’s first integrated CAN FD soft IP core and VIP package

Nikos Zervas, chief executive officer of CAST

Northwest Logic uses PCI-Xactor VIP including compliance tests to comprehensively verify NWL family of PCI Express Cores. Avery enables NWL to obtain a high level of test coverage with a reasonable level of effort. Avery is very responsive to NWL’s needs, keeps the VIP up to date against the PCIe standard, and has provided a services to help NWL accelerate its verification efforts.

Brian Daellenbach, Senior Director, Rambus Controller Group

Industry Associations & Standards