Gate-Level Parallel Simulation
- Run post-layout, SDF-based gate-level simulation using multi-core and multiple server clusters
- Speed up simulations by 3-5X
- No design changes, no testbench changes, no SDF changes
- Engines run cycle-based or lock-step synchronization
- Supports all three major simulators (Xcelium/VCS/Questa)
- Simulation analyzer tool generates design block workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy report
- Automatic coarse-grained partitioning of flat and hierarchical netlists
- Patent pending methods further optimize performance
into N-way parallel simulations
Run the same SoC top-level for all partitions. SimCluster will dynamically isolate all submodules except those actively simulating in each of the respective partitions