Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of
- SystemVerilog / UVM Verification IP portfolio
- Virtual host/embedded QEMU and VIP / RTL system co-simulation
- Semi-Formal applications for X-verification
- FPGA-assisted acceleration, FPGA prototyping tools speed adapter IPs
In 2023, Siemens acquired Avery Design Systems, furthering extending Siemens’ leadership in the verification space. Adding Avery’s impressive Verification Protocol and Compliance Test Suite offerings, critical verification IP market understanding and know-how, and eminent R&D talent enhance Siemens’ offerings across mainstream verification IP segments, while further extending Siemens verification solutions into areas such as High Performance Computing, Edge, Networking, and 3DICs. Being part of Siemens combines Avery’s products and Siemens‘ Questa verification IP offerings, enabling continued support of verification engineers across the entire spectrum of simulation solutions.
More about Avery’s management team and advisors here.