Avery Design Systems Targets Low Power Retention Register Synthesis
ANDOVER, MA., May 28, 2014 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today introduced a new low power design optimization solution, RetentSYN, targeting area and leakage power reduction in low power designs. RetentSYN’s patent pending solution automatically identifies registers that do not require retention during power-down cycles and generates optimized UPF.
RetentSYN utilizes formal analysis of a design’s various power state transition sequences and function test sequences to determine which registers need retention and which do not. “Using retention registers can be very costly to designs. Providing an automated tool for retention register selection enables greater area and leakage power reduction compared to results from manually selecting registers”, said Chris Browy, VP sales and marketing of Avery Design.
RetentSYN performs power-aware symbolic simulation of RTL or netlists based on analyzing the design’s initial UPF and provided power state transition sequences and function test sequences captured by one or more regular RTL or gate-level logic simulation waveforms. To determine which registers in any one of the powered-down blocks require retention, RetentSYN constructs a proof that indicates if a non-retained register corrupted to ‘X” during power-down will propagate to outputs or other state registers thus altering the design state compared to fully retained designs. An optimized UPF is generated. Users can also perform what if analysis to verify their manual retention selections are valid. RetentSYN supports chip-level analysis involving long power sequences using automated design and temporal partitioning methods.
Partial retention designs cut area and leakage power considerably compared to full retention designs. Retention register-based designs also provide for the fastest power-up times compared to other alternatives such as scan-based retention approaches.
Visit us at the Design Automation Conference (DAC) June 2-4 in booth #1225.
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Avery Design Systems