Avery Design Systems Announces UFS Host Controller UFSHCI Verification Solution
ANDOVER, MA., October 8, 2013 – Avery Design Systems Inc., a leader in verification IP, today announced availability of its UFS Host Controller Interface (JESD223 UFSHCI) verification solution supporting the latest embedded mobile storage solutions comprised of MIPI UniPro and M-PHY, and JEDEC UFS specifications.
The new release of MIPI-Xactor allows design and verification engineers to quickly and extensively test the functionality of both UFSHCI-compliant host controllers and UFS devices.
Avery provides a complete verification solution consisting of SystemVerilog UVM/OVM/VMM compliant models and environment, protocol checkers, directed and random compliance test suites, and reference verification frameworks. Additional advanced debug features include multi-level analyzer trackers to visualize data and control flow through the protocol stacks.
Key Features
- UFS Host Controller Driver (UFSHCD) model
– Emulates UFSHCI host driver including host initialization steps
– Supports random controller and device configuration for comprehensive verification
– Supports virtual hardware adaptor interface to UFSHCI controller via AMBA or PCIe local bus interface
– Supports 4 main SAPs: UIO_SAP, UDM_SAP, UTP_CMD_SAP, UTP_TM_SAP
– Supports command sets
- Native UFS
- SCSI SPC-4, SBC-3, SAM-5
- UIC commands
– Abstract transaction classes model UTRL, UTMRL, UTRD, UTMRD, and UCD, and UPIUs
– Supports random SGL generation
– Multiple protocol analyzer trackers for UTP-level, AMBA, SAPs, UniPro layer-level, and symbol level
– Comprehensive protocol checking
– Avery and JEDEC UFS Test Spec (JESD224) compliance testsuites
- UniPro model
– Emulates UniPro protocol stack layers and M-PHY
– Supports all service primitives (SAP) and service data units (x_SDU)
– DME User supports all sequences of control, configuration, and status primitives
– Transport service
- Allocates connections between CPorts
- Schedules message transfers between CPort Users
– Supports CPort signal interface
– Supports UniPro Test Feature
- M-PHY
– Multiple LANE provisions
– HS_MODE, all GEARs
– LS-MODE NRZ and PWM signalling schemes, all GEARs
– Multiple power saving modes
Key BFM Features
- Layered environment based on family of SystemVerilog classes and methods
- Abstract data model for transfer, packet, and descriptor types
- Drivers, event callbacks, and scoreboard options automate status and result checking
- Robust error injection enables modifying, adding, or deleting frames
- UFS and UniPro transaction trackers (command and packet exchanges)
- Throughput calculation for performance analysis
- Random scenario generation with constraints stress design operation
- Directed tests for focused functional compliance testing including UFS and SCSI commands and UFS and UniPro power modes
- Functional coverage monitoring of scenario cases
- Comprehensive protocol checking
- UVM support