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Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity

Tewksbury, MA., June 21, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications. eTopus designs ultra-high speed mixed-signal semiconductor solutions for high-performance…

Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol 

Avery to offer VIP, verification aids to enable design with recently-announced die-to-die interface standard backed by industry leaders  Tewksbury, MA – June 15, 2022 – Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage…

Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express

Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking about DPU architecture for…

PCI Express VIP from Avery Design Systems Selected by Fungible for Ensuring Compliance, Connectivity in Hyperscale Data Centers

Tewksbury, MA., Feb 28, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, to ensure compliance and connectivity of its Fungible Data Processing Unit™ (DPU). The Fungible DPU™ is an industry-first and addresses the most…

AI expands HBM footprint

High bandwidth memory (HBM) is becoming more mainstream. With the latest iteration’s specifications approved, vendors in the ecosystem are gearing to make sure it can be implemented so customers can begin to design, test and deploy systems. Avery Design Systems has built a verification platform based on its own tested verification IP (VIP) portfolio to…