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PCIe Verification IP Solutions

Avery PCI Express VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic generation, robust TL/DLL/PHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation. Avery compliance testsuites offer effective core-through-chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.


  • PCIe Gen1-6 dual mode RC/EP, Retimer, and PIPE PHY and optional UCIe PHY driver BFMs
  • Compliance test suites
  • User Guide


  • Dynamically configurable BFMs supporting root complex, endpoint, and switch. Compile once and select configuration at runtime as RC or EP
  • BFM randomly configures DUT during enumeration to test more supported configurations in less time such as randomizing equalization (coefficients, presets, reject coefficients) where many PHY layer issues are found
  • Root complex BFM mirrors DUT configuration enabling context-based validation
  • Inject errors at all layers using callbacks and packet operations such as nullify, drop, nak, field override, etc.
  • Transaction class and multi-function request/completion queues makes modeling large, high bandwidth, interleaved, delayed traffic request and completion streams easy. Stream TLPs based on random source request function and target memory and config space.
  • SV constraint set on all packet and transaction classes generates rich set of normal and error packets
  • Multi-level protocol trackers (TL, DLL, PL) makes debugging faster
  • Functional coverage tracks TLP/DLLP commands and device states
  • Comprehensive assertions track PCI-SIG compliance checklist coverage and isolate DUT bugs faster
  • Comprehensive directed and constrained random compliance test suite achieves high protocol coverage

Protocol Family Standard Organization Sub Protocol Models
PCIe PCI-SIG PCIe 6.0r0.9
PCI-SIG PCIe_Test_Spec_Config_Space_5.0r0.7
PCI-SIG PCIe_Test_Spec_Link_Trans_5.0r0.7
CPI Intel CPI 1.0
SFI Intel SFI 1.0
LPIF Intel LPIF 1.0
PIPE Intel PIPE 6.0
UCIe UCIe UCIe 1.0

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