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I3C / I2C / SMBus VIP

I3C bus topology comprised of I2C devices and I3C devices

I3C-Xactor is a comprehensive memory VIP solution portfolio for I3C and I2C s used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. I3C-Xactor implements a complete set of models, protocol checkers, and compliance testsuite in 100% native SystemVerilog and UVM.


  • I3C/I2C/SMBus master and slave BFMs
  • Compliance testsuite
  • User Guide


  • Supports I3C Basic and Full specifications and I3C Host Controller Interface (HCI)
  • Supports I3C Debug and JESD 403-1 SidebandBus
  • Supports I2C and SMBus 3.0
  • Dual mode VIP models supporting master and slave
  • Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage for master and slave
  • Comprehensive protocol checking
  • Configurable reference testbench to plug in any DUT with I3C and I2C devices
  • Native SystemVerilog/UVM implementation
  • Open and unencrypted timing class models all timing parameters (randomize, modifiable)
  • Supports I3C/I2C/SMBus command class models, all types
  • Callbacks support error detection and injection
  • SV constraint set on all transaction classes generates rich set of normal and error packets
  • Master randomly configures slaves
  • Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster
  • Tracker log monitors all levels and improves debug
Protocol Family Standard Organization Sub Protocol Models
SMBUS System Management Interface Forum SMBUS Ver 3.1
I2C NXP UM10204
I3C MIPI I3C 1.1
MIPI I3C Basic 1.1
MIPI I3C Debug 1.0

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