DisplayPort / eDP VIP

Comprehensive support for DP/eDP source and sink design verification

DisplayPort VIP is a comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs. DP VIP implements a complete set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM

Deliverables

  • Source, Sink, Repeater BFMs
  • Compliance Testsuites
  • User Guide

Features

  • Verification of transmitter/source, repeater, and bridge and PHY designs
  • SST, MSO, and MST multi-stream transport
  • AUX channel services
  • Audio-Audio and Audio-Video synchronization
  • ALPM
  • Supports I2C over AUX CH and EDID
  • Supports DPCD registers
  • PHY features include 1-4 lanes, inter-lane skew, receiver de-skew
  • Adaptive Sync
  • Supports SSC
  • Supports packing of all video RGB, YCBCR444,
  • YCBCR422 and RAW color formats and frame rates
  • HPD based link training
  • Supports HDCP 1.4, 2.2, 2.3 SST and MST
  • Supports Display Stream Compression (DSC)
  • Supports Display Parallel Interface (DPI) for pixel stream interface
  • SPD and Main Stream Attribute (MSA) packets
  • Comprehensive protocol checking and coverage report
  • Functional traffic, error, and operational and power modes coverage
  • Protocol analyzer tracker report at all layers
  • Error injection and scoreboarding
  • Native SystemVerilog UVM
  • Standards-based and custom Avery Conformance testsuites
  • Verified with multiple IP vendor partners
Protocol Family Standard Organization Sub Protocol Models
DP VESA DP 2.0.1
PICSIG PIPE 4.2
VESA VESA DisplayPort v1.4a Link Layer Compliance Test Specification(Link CTS) Revision 1.0
VESA VESA DisplayPort v1.4a PHY Layer Compliance Test Specification (PHY CTS) Revision 1.
eDP VESA eDP 1.4b
VESA VESA eDP Link Layer Compliance Test Guide v1.0
VESA VESA eDP Source PHY Compliance Test Guide v1.0
VESA HDCP 1.4/1.3, HDCP 2.3/2.2
CEA CEA-861-F
DSC VESA DSC 1.2
DPI MIPI DPI-2

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