DDR Memory Verification (VIP)

DDR memory VIP portfolio is a comprehensive memory VIP solution portfolio for DDR5/4, LPDDR5/4, RDIMM/LRDIMM/NVDIMM, DFI-PHY used by SoC and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers to ensure comprehensive verification and protocol and timing compliance. The DDR VIP implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.

Deliverables

  • DDR models support JEDEC, MIPI, and DFI-PHY standards
  • Flexible and unencrypted SystemVerilog timing class models all timing parameters
  • Dynamic runtime configuration of memory parameters between DDR (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter
  • Comprehensive protocol checks for all DDR commands and sequences, ODT, write leveling, temp control, data mask and DBI, ZQ calibration, Gear Down, Row hammer ACT threshold, and detailed timing checks including jitter and write DQS checks
  • Optional DDR commands supported for DLL off-mode operations, Input clock frequency change,
  • Extended temperature usage
  • Back door block read/write access of sparse memory and MRS registers
  • Supports active and monitor model modes
  • Extensive callbacks for error injection
  • Tracker log monitors improves debug including MRS configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers
  • Interposer style performance metrics and functional coverage tracks bus utilization, bandwidth, command-command latency including bank and bank group analysis, and MR modes selected to isolate performance bottlenecks and ensure all functional modes have been verified
  • Vendors supported: Micron, Samsung, Hynix

Features

  • DDR models support JEDEC Low Power Memory Device and DDR4 DRAM (JESD79-4)
  • Flexible and unencypted SystemVerilog timing class models all timing parameters
  • Dynamic runtime configuration of memory parameters between DDR4/3/2 (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter
  • Comprehensive protocol checks for all DDR4 commands and sequences, ODT, write leveling, temp control, data mask and DBI, ZQ calibration, Gear Down, Row hammer ACT threshold, and detailed timing checks including jitter and write DQS checks
  • Optional DDR commands supported for DLL off-mode operations, Input clock frequency change,
  • Extended temperature usage
  • Back door block read/write access of sparse memory and MRS registers
  • Supports active and monitor model modes
  • Extensive callbacks for error injection
  • Tracker log monitors improves debug including MRS configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers
  • Interposer style performance metrics and functional coverage tracks bus utilization, bandwidth, command-command latency including bank and bank group analysis, and MR modes selected to isolate performance bottlenecks and ensure all functional modes have been verified
  • Vendors supported: Micron, Samsung, Hynix
Protocol Family Standard Organization Sub Protocol Models
DDR3 JEDEC DRAM JESD79-3F
JEDEC RCD JESD82-29A
JEDEC MB JESD82-xx v0.95c
JEDEC RDIMM 4.20.20-1
JEDEC LRDIMM 4.20.24-1
LPDDR5 JEDEC JESD209-5
LPDDR4 JEDEC JESD209-4.1D
GDDR6 JEDEC JESD250C
DDR5 JEDEC DRAM JESD79-5A
JEDEC DFI-PHY DFI 5.0
JEDEC RCD JESD82-512
JEDEC DB JESD82-522
JEDEC SidebandBus JESD403-1.01, I3C 1.1

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