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Suresh Sankaralingam, head of DV and Emulation, Astera Labs

Avery’s CXL virtual platform and VIP co-simulation solution helped reduce our validation time as we were able to perform extensive pre-silicon verification on our Leo Memory Connectivity Platform that supports CXL 2.0 and 1.1 technologies, and we are ready for real-world deployment. We look forward to utilizing a similar approach as we evolve next generation CXL designs