DDR-Xactor is a comprehensive memory VIP solution portfolio for DDR4/3, LPDDR3/2, RDIMM/LRDIMM, DFI-PHY used by SoC and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers to ensure comprehensive verification and protocol and timing compliance. DDR-Xactor implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.



  • User Guide

Tech Specs

Short description:DFI-PHY 3.1 VIP
Provider:Avery Design Systems
Languages Supported:SystemVerilog, Verilog
Compliant Standard:DFI-PHY 3.1

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  • Stand-alone DFI-PHY model supporting active and monitor model modes

  • Supports all read/write/control transfers between MC and SDRAM

  • Supports all interfaces including Read/Write/Control, PHY Update including DFI-PHY initiated PHY Updates, Status, training including MC and PHY modes, low power, supports all frequency ratios (1:1, 1:2, 1:4), clock disable, and reset modes

  • Timing modes including random timing parameter setup, quicksim modes, and supports TX skew and jitter

  • Interfaces to memory controller and either SDRAM or RDIMM

  • Memory controller model and DFI-PHY compliance testsuite provide complete solution to verify DFI-PHY digital functionality

  • Comprehensive protocol and timing checks
    Tracker log monitors all levels and improves debug