CSI/DSI-Xactor is a comprehensive VIP solution for CSI-2, DSI-2, D-PHY, and C-PHY transmitter and receiver designs. CSI/DSI-Xactor implements a complete set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM.


  • CSI-2 BFM

  • DSI-2 BFM



  • Compliance testsuite

  • User Guide

Tech Specs

Short description:CSI-2/DSI-2 Verification IP
Provider:Avery Design Systems
Languages Supported:SystemVerilog, Verilog
Compliant Standard:CSI-2 v2.0r02 DSI-2 v1.0r02 C-PHY v1.2r02 D-PHY v2.1r02

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  • Verification of both transmitter/source and receiver/sink and PHY designs DSI-2 with C-PHY and D-PHY, CSI-2 with C-PHY and D-PHY

  • Automated dynamic Video and Audio traffic generation and PHY bit rate clock generation delivering fully accurate frame synchronization timing of multiple video and audio sources based on various shaping parameters including random receiver/sink device peripheral parameter set, interleaved/multiple packet control, interleaved frames control, line and frame blanking intervals

  • Standard DSC extensions

  • Comprehensive protocol checking and coverage report

  • Functional traffic, error, and operational and power modes coverage

  • Standard DSC extensions

  • Comprehensive protocol checking and coverage reports

  • Protocol analyzer tracker report at all layers

  • Error injection and scoreboarding supported through Automated Frame Generation common callback for layer-specific

  • Inspection and error injection using methods to in-line

  • Modify, drop, inject packet ahead/behind, force next state

  • Standards-based and custom Avery Conformance testsuites

  • Verified with multiple IP vendor partner

  • Perform receiver configuration

  • Execute sleep modes including SLM sequence

  • Perform receiver error detection

  • DSI-2 DSC 1.1 supported

  • CSI-2 data compression for RAW Data types supported

  • CSI TX/RX and C-PHY/D-PHY Conformance tests

  • D-PHY and C-PHY model support TX and RX HS, LP, and FEN, CNN

  • System power-up and initialization

  • Bidirectional signalling control mode and video mode systems

  • Read, ACK, Error reporting

  • Forward escape ULPS for sleep modes

  • Multi-lane distribution and merging

  • Multi-lane interoperability (TX X-lanes, RX Y-lanes)

  • D-PHY specific deskew calibration including bypass and periodic

  • C-PHY specific enable/Disable 3-phase encoding