Pre-Silicon Verification – The Newest Approach to Accelerating Time-to-Market of Advanced Computing Capabilities

Chris Browy, Vice President of Worldwide Sales and Marketing of Avery Design Systems, is a go-to expert on all things functional verification.

Avery, a well-established provider of functional verification solutions, has been around since 1998 supporting a growing and complementary line of SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for system-on-chip (SoC) verification. It is also a member of the ESD Alliance, a SEMI Technology Community.

I recently caught up with Browy and asked him how an engineer verifies and ensures the compliance of new chip designs with emerging standards when there is no proven system platform yet to support those standards. His informed response kicked off our conversation. 

Avery logo“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to approach this challenge and get designs verified ahead of the curve of new standards,” Browy said.

Smith: What is pre-silicon certification and why is it important?

Browy: Historically, new designs are verified using a combination of logic simulation, VIP, hardware emulation or FPGA prototyping. But true design certification wasn’t possible until the prototype silicon was available.

What we are seeing now is a shift left paradigm emerging that targets pre-silicon certification of SoCs and peripherals for Intel and Arm systems. This requires system-level hardware/software co-verification more than ever. The ability to certify the design prior to silicon availability is a game changer for accelerating time-to-market.

Smith: What new technologies or approaches are needed to enable pre-silicon certification?

Browy: VIP plays a key role in this new paradigm. Next-generation VIP must move beyond the traditional role of verification and SoC hardware and take into account the complete system – but not in the abstract sense like virtual prototyping does. What is needed is a way to create accurate pre-silicon virtual platforms running OS, firmware, and hardware so that everything can be integrated and validated earlier to accelerate development and design refinements and efficiently resolve bugs. Hardware-assisted verification provided by emulators and FPGA prototyping remain essential in this scheme.

Smith: Is pre-silicon verification and certification already in use today?

Browy: Yes. For example, consider the emerging Compute Express Link (CXL) standard. It is the latest and probably most significant standard driving the future of compute into composable, disaggregated systems for high-performance data centers involving storage class memory, AI acceleration, Smart NIC, and DPUs and GPUs.

VerifiedFirst, access to pre-silicon functionality means designers can get out in front of CXL commercialization by using virtual platforms to perform system-level verification before the physical components needed for FPGA prototyping or emulation are available. Second, while those approaches are fast and comprehensive, they are expensive, extremely time-consuming and arduous, especially during the debugging and design revision process. Using a VIP-enabled virtualization strategy, designers can quickly iterate before a final verification run with hardware based tools. Compliance testing is also another benefit of virtualization, allowing developers to ensure they are complying with the standard.

Smith: What is involved in putting together a virtual platform for pre-silicon certification of standard protocols and supporting hardware-software verification. Do you have any specific examples of how that can work?

Browy: Take an example that most everyone is familiar with – the solid state drives (SSD or NVMe) in many products including smartphones, laptops, desktops and enterprise servers. These devices have significant embedded processing firmware for NVMe and Flash memory portions, on top of the host Windows or Linux OS drivers. For most general-purpose applications, Quick Emulator (QEMU) (an open source machine emulator and virtualizer) provides a virtual platform to support various hardware and processor targets from x86 hosts to embedded Arm and RISC-V systems.

When integrated into a SystemVerilog co-simulation framework, a complete SSD system can be booted and functionally validated. The SoC RTL testbench comprised of the NVMe SSD RTL and PCIe and AMBA VIPs can be co-simulated with one or more QEMU instances running the embedded processors and SSD firmware as well as the x86 host platform running Linux kernel and SSD host drivers.
 

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Smith: Who is responsible for ultimately ensuring compliance with new versions of standards like CXL, PCIe and NVMe?

Browy: Successful implementation of emerging new standards relies on an ecosystem that includes the standards organizations themselves, the major standards champions in the semiconductor and systems areas, tool and IP suppliers and third-party compliance groups working together to ensure interoperability. At Avery, we focus heavily on supporting compliance tools and hardware platforms used in compliance workshops. These virtual platforms enable chip designers to develop and validate system functionality and performance and ensure compliance with emerging standards prior to the availability of first silicon.

About Chris Browy

Chris Browy headshotChris Browy is Vice President of Worldwide Sales and Marketing and co-founder at Avery Design Systems in Tewksbury, Mass. Prior to his last two decades with Avery, from 1989 to 1998, Browy held various positions at Cadence Design Systems including Director of ASIC Design Services, Director of Top-down IC Design Practice, and marketing manager for synthesis, timing analysis, and test products. Prior to 1989, Chris held numerous other positions in applications engineering and hardware systems development. He has been responsible for system and ASIC design projects involving large-scale ATM switching systems, non-linear digital video editing systems, and massively parallel multiprocessors. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984.

Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

By Bob Smith – Original Article


Company Contact: 

Christopher Browy 

cbrowy@avery-design.com 

(978) 851-3627

Press Contact: 

Mike Sottak 

mike@wiredislandpr.com 

(650) 248-9597