News

NVM-Express Verification IP

Avery Design Systems Adds NVM Express to Storage Standards Verification IP Solutions

ANDOVER, MA., May 29, 2012 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its NVM-Xactor verification IP targeting Non-Volatile Memory Express (NVMe) for high performance PCIe-based SSDs.  NVM-Xactor extends Avery’s portfolio of storage-related VIP which also includes USB Attached SCSI (UASP), USB Mass Storage Class Bulk-Only Transport (BOT), MIPI…

Avery Design Systems Unveils DDR4 and DFI-PHY Verification IP Solution

ANDOVER, MA., March 22, 2012 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its DDR-Xactor verification IP providing DDR and LPDDR memory models and a complete DFI-PHY verification solution. DDR-Xactor VIP includes ·        SDRAM memory chip and DIMM models ·        DFI-PHY model ·        Simple AXI-based memory controller model ·        Compliance testsuite ·        Timing…

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification

ANDOVER, MA., March 22, 2012 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, SimXACT, targeting comprehensive X propagation analysis including gate-level X pessimism analysis and automatic correction of gate-level simulation results, and XVER, X optimism analysis of RTL simulation. The inherent limitations of…

MIPI Unipro Verification IP

Avery Design Systems Announces MIPI UniPro and UFS Verification Solution

ANDOVER, MA., January 11, 2012 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced the MIPI-Xactor verification solution supporting the MIPI UniPro and M-PHY, and JEDEC UFS specifications. MIPI-Xactor is a complete verification solution consisting of SystemVerilog UVM/OVM/VMM compliant Bus Functional Models (BFM), protocol checkers, directed and random compliance test suites,…

Northwest Logic and Avery Design Systems Successfully Team on PCI Express 3.0 Solutions

ANDOVER, MA., August 8, 2011 – Northwest Logic Inc., a leader in high-performance digital IP Cores, and Avery Design Systems, a leader in Verification IP (VIP) solutions, today announced Northwest Logic’s Expresso 3.0 solutions for PCI Express® (PCIe®) for Endpoint, Root Complex, and Switch have been fully verified and deployed to customers based on Avery’s PCI-Xactor…