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Avery Design Systems and Rambus Extend Memory Model and PCIe® VIP Collaboration

Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory…

Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systemsAvery PCIe and CXL Verification IP enabled Astera Labs to get to market faster Tewksbury, MA., April 28, 2021 Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions…

Avery Design Debuts CXL™ 2.0 System-level VIP Simulation Solution

Tewksbury, MA., April 15, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced its CXLTM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL…

NUVIA Selects Avery Design for Next Generation PCIe® Verification

March 12, 2021 03:23 PM Eastern Standard Time TEWKSBURY, Mass.–(BUSINESS WIRE)–Avery Design Systems, leader in functional verification solutions today announced NUVIA who is reimagining silicon in a new way, creating compute platforms that redefine performance for the modern data center, has deployed Avery PCIe Verification IP (VIP) for subsystem and SoC verification. “After evaluating several…

Avery Design Announces CXL 2.0 VIP

Tewksbury, MA., January 22, 2021 — Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP.  Computer Express LinkTM (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices   Avery provides a…

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe® VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMeTM SSD and PCIe® Designs

Tewksbury, MA., November 9, 2020 — Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMeTM SSD and PCIe® designs using QEMU virtual host to SystemVerilog PCIe VIP co-simulation thus enabling the functional validation of complete NVMe and PCIe hardware-software SoC designs using industry standard conformance and performance benchmarking software applications running…