News

Avery Design Introduces CXL VIP

Tewksbury, MA., September 23, 2019 — Avery Design Systems, leader in functional verification solutions today announced CXL VIP supporting the latest CXL Specification 1.1 from the Compute Express Link (CXL) open standard. “Built upon our well-established PCI Express® (PCIe®) verification IP infrastructure, the CXL supports PCIe 5.0 physical and electrical interface (PIPE 5.1) to provide…

Avery Design Partners with Marquee Semiconductor to Provide Sales, Support in India, and Deepens its Relationship to Prime Marquee’s SoC Solution Platform

Tewksbury, MA., September 23, 2019 — Avery Design Systems, leader in functional verification solutions, and Marquee Semiconductor, a Spec-to-Silicon SOC solution company, today announced a broad joint collaboration to deliver innovative SOC solutions incorporating sales and support for Avery verification IP (VIP) and EDA products and Marquee design IP for analog/RF and NOC along with…

Avery Design Systems Announces SimAccel FPGA Accelerator

TEWKSBURY, MA., August 2, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of the SimAccel FPGA-based accelerator to achieve 100-1000X speed up over simulation-based verification. “As SoCs get larger the feasibility of performing comprehensive SoC verification using purely simulation and without hardware-software co-verification is less and less…

Avery Design Systems Announces SimRegress and SimCompare

TEWKSBURY, MA., June 28, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimRegress and SimCompare for improved simulation verification productivity. SimRegress provides the ability to capture and replay the simulation testbench stimulus without having to run the full testbench thus supporting improved methods for 3rd party…

Astera Labs Verifies Its System-Aware PCI Express® 5.0 Smart Retimer Using Avery Design Systems PCIe® 5.0 Verification IP

Tewksbury, MA., June 18, 2019 — Avery Design Systems, leader in functional verification solutions today announced that Astera Labs successfully utilized Avery’s Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer. The Avery PCIe 5.0 VIP supports models and testsuites for the newly ratified…

Avery Design Systems Announces SymXprop for X Accurate RTL Simulation

TEWKSBURY, MA., May 30, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SymXprop that performs high accuracy semi-formal based RTL X handling to eliminate the inherent inaccuracies in logic simulators. “Design practices involving partial reset, uninitialized memories, and clock and power gating expose SystemVerilog’s inaccurate RTL…

Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations

TEWKSBURY, MA., May 30, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimCluster GLS that performs gate-level parallel simulation to achieve 3-5X speed up of sign-off simulations. “As chips get larger the feasibility of performing post-layout SDF-based gate-level simulation gets harder and harder,” said Chris Browy,…