News

NUVIA Selects Avery Design for Next Generation PCIe® Verification

March 12, 2021 03:23 PM Eastern Standard Time TEWKSBURY, Mass.–(BUSINESS WIRE)–Avery Design Systems, leader in functional verification solutions today announced NUVIA who is reimagining silicon in a new way, creating compute platforms that redefine performance for the modern data center, has deployed Avery PCIe Verification IP (VIP) for subsystem and SoC verification. “After evaluating several…

Avery Design Announces CXL 2.0 VIP

Tewksbury, MA., January 22, 2021 — Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP.  Computer Express LinkTM (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices   Avery provides a…

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe® VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMeTM SSD and PCIe® Designs

Tewksbury, MA., November 9, 2020 — Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMeTM SSD and PCIe® designs using QEMU virtual host to SystemVerilog PCIe VIP co-simulation thus enabling the functional validation of complete NVMe and PCIe hardware-software SoC designs using industry standard conformance and performance benchmarking software applications running…

PLDA® Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL®, PCIe® 6.0 or Gen-Z® Interconnect

PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to…

ESD Alliance Welcomes Avery Design Systems to Member Community

MILPITAS, Calif., Feb. 25, 2020 (GLOBE NEWSWIRE) — The Electronic System Design Alliance, a SEMI Strategic Technology Community representing members in the electronic system and semiconductor design ecosystem, today welcomed Avery Design Systems as a member after its 10-member Governing Council approved Avery’s membership application. Already a member of SEMI, the global industry association representing the worldwide electronics product design…

Avery’s Partner Mobiveil Announces Availability of Compute Express Link (CXL) IP (COMPEX) for High-Performance Applications

MILPITAS, Calif., Feb. 24, 2020 (GLOBE NEWSWIRE) — Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced availability of COMPEX Compute Express Link™ (CXL) IP. The COMPEX controller is designed to the CXL 1.1 specification and supports Host and Type 1, Type 2 and Type 3 device types.…