Avery Design Systems Takes Focus on MIPI CSI and DSI VIP Solutions
TEWKSBURY, MA., June 8, 2015 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of MIPI VIP supporting the DSI-2, CSI-2 v2.0, C-PHY v1.1, and D-PHY v1.2 standards. This expands Avery’s comprehensive MIPI VIP portfolio which already includes UFS, UFSHCI, Unipro, M-PHY, and Soundwire. CSI and DSI VIP supports…
Avery Design Systems Unveils DDR4 3DS LRDIMM VIP Solution
TEWKSBURY, MA., June 8, 2015 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of DDR4 3D Stacking (3DS) support for its DDR4 memory chip and LRDIMM Verification IP (VIP) models and compliance testsuites. DDR-Xactor VIP supports: • SDRAM memory chip models • RDIMM/LRDIMM models including RCD and DB…
PLDA and Avery Design Systems Cooperate on PCI Express
TEWKSBURY, MA, March 2, 2015 – Avery Design Systems Inc., a leader in verification IP, today announced PLDA and Avery Design Systems have engaged in collaboration to facilitate interoperability of PCI-Xactor VIP and XpressRICH IP and perform extended compliance validation using Avery PCIe compliance test-suite. “We have been pleased to collaborate with Avery Design to…
Avery Design Systems Revs PCIe and eMMC VIP and Introduces VIPs for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD
ANDOVER, MA., May 28, 2014 – Avery Design Systems Inc., a leader in verification IP, today announced availability of a major new release of the flagship PCIe VIP, major VIP update for eMMC 5.X, and new VIP introductions for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD. The Avery VIP portfolio is now 100% implemented in…
Avery Design Systems Targets Low Power Retention Register Synthesis
ANDOVER, MA., May 28, 2014 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today introduced a new low power design optimization solution, RetentSYN, targeting area and leakage power reduction in low power designs. RetentSYN’s patent pending solution automatically identifies registers that do not require retention during power-down cycles and generates optimized…
Avery Design and BaySand Team to Deliver IP Solutions for TeneX Configurable SoC
SoC designers gain high performance and fast turnaround at low cost and reduced risk ANDOVER, MA., January 9, 2014 – Avery Design Systems and BaySand today announced a cooperative effort to deliver comprehensive IP solutions for BaySand’s breakthrough TeneX configurable System on Chip (SoC) solution based on innovative Metal Configurable Standard Cell (MCSC) technology. The cooperation…
Avery Announces UFS Host Controller UFSHCI Verification Solution
Avery Design Systems Announces UFS Host Controller UFSHCI Verification Solution ANDOVER, MA., October 8, 2013 – Avery Design Systems Inc., a leader in verification IP, today announced availability of its UFS Host Controller Interface (JESD223 UFSHCI) verification solution supporting the latest embedded mobile storage solutions comprised of MIPI UniPro and M-PHY, and JEDEC UFS…