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Avery Design Systems Announces SimXACT 5.0 for Improved X-Verification

TEWKSBURY, MA., February 23, 2018 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of release 5.0 of its patented SimXACT analysis solutions including major new features for analyzing and automatically eliminating X bugs in gate-level design simulation.

SimXACT automates the tedious process of analyzing X propagations in gate-level simulations due to RTL vs gate-level mismatches arising from X-optimism problems and gate-level simulator X-pessimism handling in glue logic and gated clocking and overly pessimistic library cell modelling. SimXACT’s hydrid formal analysis runs with your normal logic simulator and proves and then on-the-fly fixes any false Xs arising from X pessimism during the actual simulation run. SimXACT also provides X analysis to debug X bugs from RTL vs gate-level simulation mismatches.

Highlights of the 5.0 release include:

  • X glitch detection features to root cause and fix Xs generated due to delta cycle glitches that are difficult to debug because the glitches may not show up in the waveform
  • Testpoint connectivity analysis checks for force statements from testbench finding GLS issues due to ports being optimized out
  • New patent pending analysis and fix optimization engine that increases performance up to 10X
  • ECO flow reverifies fixes from prior SimXACT runs after small netlist changes for better turnaround times
  • SoC flow for analyzing the DUT block-by-block in parallel to improve performance and find X issues more quickly
  • Cadence Xcelium now supported
  • X Trace Viewer automates root causing X through mixed level behavioral, RTL, and gate-level designs

X Trace Viewer highlights:

  • Root cause real Xs more quickly and effectively causing designs to operate non-deterministically coming out of reset or during normal operation modes
  • Supports one-step automatic sequential backtracing through hierarchical, mixed gate-level, RTL, and behavioral designs showing full X propagation history times over multiple clock cycles
  • Integrates with Verdi, Simvision, Questa to automatically scope Xs in source code and waveform views for full X propagation references
  • Supports interactive, command line, and batch modes
  • Uses structural RTL and formal-augmented X gate-level backtracing identifying real “controlling” functional support only keeping X clutter down

  • Provides FF corruption report for identifying X candidates requiring analysis

Visit us at the DVCon San Jose during February 26-28.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at