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Avery Design Systems Announces MIPI UniPro and UFS Verification Solution

MIPI Unipro Verification IP

ANDOVER, MA., January 11, 2012 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced the MIPI-Xactor verification solution supporting the MIPI UniPro and M-PHY, and JEDEC UFS specifications.

MIPI-Xactor is a complete verification solution consisting of SystemVerilog UVM/OVM/VMM compliant Bus Functional Models (BFM), protocol checkers, directed and random compliance test suites, and reference verification frameworks.  The MIPI-Xactor allows design and verification engineers to quickly and extensively test the functionality of UFS and UniPro/M-PHY compliant host and device controller-based designs.

“MIPI-Xactor builds on our solid foundation as a leading supplier of PCI Express and USB verification solutions to IP vendors and semiconductor companies,” said Chris Browy, vice president of sales and marketing of Avery Design Systems.  “Our solution enables designers to thoroughly verify their designs functionally adhere to the new UFS and UniPro standards and effectively pinpoint areas of non-compliance or performance bottlenecks.”

Key Features

UFS Host

        Emulates host driver and host controller

        Supports UFS DME and CPort Users

        Supports command sets

         Native UFS

         SCSI SPC-4, SBC-3, SAM-5

     UniPro Core

        Emulates UniPro protocol stack layers and M-PHY

        Supports all service primitives (SAP) and service data units (x_SDU)

        DME User supports all sequences of control, configuration, and status primitives

        Transport service

         Allocates connections between CPorts

         Schedules message transfers between CPort Users

        Supports CPort signal interface

        Supports UniPro Test Feature


        Multiple LANE provisions

        LS-MODE and HS_MODE

        LS-MODE NRZ and PWM signalling schemes

        Multiple power saving modes


Key BFM Features

  • ·         Layered environment based on family of SystemVerilog classes and methods
  • ·        Abstract data model for transfer, packet, and descriptor types
  • ·        Drivers, event callbacks, and scoreboard options automate status and result checking
  • ·        Robust error injection enables modifying, adding, or deleting frames
  • ·        UFS and UniPro transaction trackers (command and packet exchanges)
  • ·        Throughput calculation for performance analysis
  • ·        Random scenario generation with constraints stress design operation
  • ·        Directed tests for focused functional compliance testing including UFS and SCSI   commands and UFS and UniPro power modes
  • ·        Functional coverage monitoring of scenario cases
  • ·        Comprehensive protocol checking
  • ·        VMM/UVM/OVM support


About Avery Design Systems


Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, X verification, and RT-level DFT at-speed testability analysis; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, and MIPI standards; and scalable distributed parallel logic simulation.  The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at


For More Information Contact:

Chris Browy

Avery Design Systems

(978) 689-7286





SOURCE: Avery Design Systems, Inc.