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Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems Avery PCIe and CXL Verification IP enabled… Read More »Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe® VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMeTM SSD and PCIe® Designs

Tewksbury, MA., November 9, 2020 — Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMeTM SSD and PCIe® designs using… Read More »Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe® VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMeTM SSD and PCIe® Designs

Avery’s Partner Mobiveil Announces Availability of Compute Express Link (CXL) IP (COMPEX) for High-Performance Applications

MILPITAS, Calif., Feb. 24, 2020 (GLOBE NEWSWIRE) — Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced availability… Read More »Avery’s Partner Mobiveil Announces Availability of Compute Express Link (CXL) IP (COMPEX) for High-Performance Applications