QEMU Integrator

Functional validation of pre-silicon NVMeTM SSD and PCIe® systems using QEMU virtual host and SoC system co-simulation enables running industry standard host server-based conformance and performance benchmarking software applications on Linux and Windows® environments along with the PCIe-based SoC design.


System bring-up and validation using standards-based conformance and interoperability testing is now feasible across a wide range of designs - NVMe SSDs, smart NICs, PCIe switches and retimers, and a myriad of other PCIe endpoint-based peripherals. Performing an in-house “virtual” plug fest at the pre-silicon level using RTL of the SoC hardware greatly increases confidence that designs will have first pass success when going for official compliance testing. Examples include:


  • NVMe SSD validation requires executing the UNH-IOL INTERACTTM test software in addition to other performance benchmarking applications such as FIO, PMark8, and CrystalDiskMark.

  • PCIe compliance requires passing the PCI-SIG® PCIeCV and interoperability tests at a PCI-SIG Compliance Workshop.


  • Co-simulating the actual SoC RTL with a QEMU open software virtual machine allows software engineers to natively develop and build any of their custom firmware, drivers, and applications for any number of Linux or Windows platforms. Software issues can be investigated using standard debuggers (GDB and KGDB) against the cycle accurate and detailed SystemVerilog RTL representation of the SoC operation. Validation spans PCI BIOS and expansion ROM code, OS boot, custom driver initialization sequences, conformance and performance benchmarking applications.


    Hardware engineers can collaborate with software engineers to debug SoC RTL utilizing the full PCIe and NVMe VIP protocol aware debugging features resulting in reduction of both hardware and software design iterations and more rapid turnaround of bug fixes. In addition, the PCIe SystemVerilog VIP supports both TX/RX error injection that is essential to testing system operation under abnormal and error conditions at the various PCIe layers.


    Compared to co-emulation or FPGA prototyping which are generally considered both scarce and expensive commodities, a co-simulation approach can scale-up on simulation farms to 100s to 1000s of concurrent simulations thus enabling more SoC configurations of the hardware and software to be covered.




    Deliverables


    • QEMU Integrator software

    • User Guide


    Tech Specs









    Short description:Pre-silicon PCIe® and NVMe™ HW-SW SoC validation using virtual machine host and SoC RTL co-simulation
    Provider:Avery Design Systems
    Languages Supported:SystemVerilog
    Compliant Standard:PCIe 5.x , 4.0, 3.1 , PIPE 5.1
    Maturity:Production
    Availability:Now

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    Features


    • Pre-silicon PCIe® and NVMe™ HW-SW SoC validation using virtual machine host and SoC RTL co-simulation

    • Accelerate development schedules and reduce bug fix times and iterations dramatically

    • QEMU virtual host runs Linux and Windows OS incorporating custom drivers and expansion firmware and application SW

    • PCIe System VIP (SVIP) links QEMU PCI root ports to SV/UVM PCIe VIP and supports advanced features - dual root ports, bifurcation, and SR-IOV and TX/RX error injection at all protocol layers

    • Supports co-simulation and co-emulation methodologies using Avery’s industry leading PCIe VIP.

    • Supports advanced QEMU performance features, such as KVM, for optimal performance

    • Target wide range of designs - NVMe SSDs, smart NICs, PCIe switches and retimers, and any PCIe endpoints

    • Run standard conformance testing programs for in-house “virtual” plug fests

    • Run standard performance benchmarking applications to analyze SoC system running realistic workloads
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