PCIe VIP

Avery PCI Express VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic generation, robust TL/DLL/PHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.
Avery compliance testsuites offer effective core-through-chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.

Deliverables


  • PCIe dual mode RC/EP, N-port switch, and PIPE 5.1 PHY driver BFMs

  • Compliance test suites

  • User Guide


Tech Specs









Short description:PCI Express 5.0 (draft), 4.0, 3.1 VIP (PCIe)
Provider:Avery Design Systems
Languages Supported:SystemVerilog, Verilog, VHDL, C
Compliant Standard:PCIe 5.0 (draft), 4.0, 3.1 , PIPE 5.1
Maturity:Production
Availability:Now


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Features


  • Dynamically configurable BFMs supporting root complex, endpoint, and switch. Compile once and select configuration at runtime as RC or EP

  • BFM randomly configures DUT during enumeration to test more supported configurations in less time such as randomizing equalization (coefficients, presets, reject coefficients) where many PHY layer issues are found

  • Root complex BFM mirrors DUT configuration enabling context-based validation

  • Inject errors at all layers using callbacks and packet operations such as nullify, drop, nak, field override, etc.

  • Transaction class and multi-function request/completion queues makes modeling large, high bandwidth, interleaved, delayed traffic request and completion streams easy. Stream TLPs based on random source request function and target memory and config space.

  • SV constraint set on all packet and transaction classes generates rich set of normal and error packets

  • Multi-level protocol trackers (TL, DLL, PL) makes debugging faster

  • Functional coverage tracks TLP/DLLP commands and device states

  • Comprehensive assertions track PCI-SIG compliance checklist coverage and isolate DUT bugs faster

  • Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage

Additional Information:

   – Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

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