I3C-Xactor is a comprehensive memory VIP solution portfolio for I3C and I2C s used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. I3C-Xactor implements a complete set of models,protocol checkers, and compliance testsuite in 100% native SystemVerilog and UVM.
- I3C/I2C/SMBus master and slave BFMs
- Compliance testsuite
- User Guide
| Short description: | I3C 1.0 +I2C 4.0 + SMBus 2.0 VIP |
| Provider: | Avery Design Systems |
| Languages Supported: | SystemVerilog, VHDL |
| Compliant Standard: | I3C 1.0+I2C 4.0 SMBus 2.0 |
| Maturity: | Production |
| Availability: | Now |
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- Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)
- Master performs built-in functions including integration steps, Dynamic clock synchronization, Bus arbitration, Activity monitor, clock streching, and timeout detection
- Open and unencrypted timing class models all timing parameters (randomize, modifiable)
- Supports I3C/I2C/SMBus command class models all types
- Callbacks support error detection and injection
- SV constraint set on all transaction classes generates rich set of normal and error packets
- Master randomly configures slaves
- Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster
- Tracker log monitors all levels and improves debug
- Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage
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