DDR5 Memory VIP

DDR-Xactor is a comprehensive memory VIP solution portfolio for DDR5/4/3, LPDDR3/2, RDIMM/LRDIMM, DFI-PHY used by SoC and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers to ensure comprehensive verification and protocol and timing compliance. DDR-Xactor implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.

Deliverables



  • DDR5 BFMs

  • User Guide


Tech Specs









Short description:DDR5 Memory VIP
Provider:Avery Design Systems
Languages Supported:SystemVerilog, VHDL
Compliant Standard: JESED79
Maturity:Production
Availability:Now



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Features


  • DDR5 memory models support major approved and draft ballots including, for example


    • Speed bin 3200,3600 and 4000
    • Burst Length x32
    • Connectivity Test
    • DDR5 Reset and Initialization sequence
    • DDR5 Fast Zero Mode
    • CS Training
    • Read Training
    • Preamble training
    • Write Leveling Modes
    • Write enable training
    • DDR5 Density 8Gb, 16Gb, 32Gb , 64Gb
    • Write Pattern Function
    • MRS Registers based ballot definitions
    • DDR5 ZQ Calibration
    • DDR 5 command Truth Table
    • Self Refresh power down modes
    • All banks/Same Bank Refresh
    • Max Power Saving Mode
    • Mask Write

  • Flexible and unencypted SystemVerilog timing class models all timing parameters

  • Dynamic runtime configuration of memory parameters between DDR5/4/3/2 (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter
  • Comprehensive protocol checks for all DDR5 commands and sequences, ODT, write leveling, temp control, data mask and DBI, ZQ calibration, Gear Down, Row hammer ACT threshold, and detailed timing checks including jitter and write DQS checks
  • Optional DDR commands supported for DLL off-mode operations, Input clock frequency change, Extended temperature usage
  • Back door block read/write access of sparse memory and MRS registers
  • Supports active and monitor model modes
  • Extensive callbacks for error injection
  • Tracker log monitors improves debug including MRS configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers
  • Interposer style performance metrics and functional coverage tracks bus utilization, bandwidth, command-command latency including bank and bank group analysis, and MR modes selected to isolate performance bottlenecks and ensure all functional modes have been verified
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