DDR-Xactor is a comprehensive memory VIP solution portfolio for DDR4/3, LPDDR3/2, RDIMM, LRDIMM (including 3DS), DFI-PHY used by SoC and memory controller designers using the external SDRAM and DIMM memory components and DFI-PHY developers to ensure comprehensive verification and protocol and timing compliance. DDR-Xactor implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.
- RDIMM BFM
- LRDIMM BFM
- RCD BFM
- DB BFM
- User Guide
| Short description: | DDR RDIMM + LRDIMM VIP |
| Provider: | Avery Design Systems |
| Languages Supported: | SystemVerilog, VHDL |
| Compliant Standard: | JEDEC DDR4 SDRAM Registered DIMM Design Specification (Rev 1.0), RCD (DDR |
| Maturity: | Production |
| Availability: | Now |
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- Supports JEDEC DDR4 SDRAM Registered DIMM Design Specification (Rev 1.0), RCD (DDR4RCD02), DB (DDR4DB02), and I2c ver 4.0 DDR4 register I2C Bus Interface
- Provides configurable RDIMM/LRDIMM topologies for programmable number of ranks and slices of all components including RCD, DB, DRAM
- Supports bit, nibble, and word flyby delays and jitter: RCD to DRAM (LRDIMM/RDIMM), DB to DRAM (LRDIMM)
- Supports DRAM, RCD, and DB callbacks to control error insertion
Supports RDIMM features including DQ mapping, address mirroring, Alert_n signalling
- Supports DB features including initialization, dual frequency support, clock frequency change, MRS and BCW register accesses, training, transparent mode, ZQ calibration
- Supports RCD features including initialization, parity, power saving modes, dual frequency support, output inversion, ZQ calibration, latency equalization, and CA bus training, RC access, and I2C bus interface, and reset modes
- Memory controller model and RDIMM/LRDIMM compliance testsuite verify RCD and DB modes of operation
- Comprehensive protocol and timing checks
- Supports active and monitor model modes
- Tracker log monitors all levels and improves debug
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