SimXACT – Gate Simulation Productivity and Analysis Technology

SimXACT’s innovative analysis technology, enables much quicker gate-level simulation bring-up by using formal analysis dynmically during simulation to automatically eliminate the noise of false Xs (X-pessimism and glitch), zero-delay race conditions, library modeling errors, and isolates hard to diagnose connectivity problems.

SimXACT provides better utilities to debug and isolate the source of remaining real X's that cause gate simulation to fail


  • Eliminates X-pessimism in GLS

    • Formal-enhanced logic simulation dynamically performs X-pessimism analysis and repair on the fly

      Analyzes X propagation in datapath and gated clock logic

      False X fixes reusable on subsequent simulation runs with no tool or license overhead

      Supports hierarchical flow for large designs by analyzing the DUT block-by-block, in parallel

  • Eliminate race conditions in 0-delay GLS

    • 0-delay GLS may demonstrate race conditions, especially in designs with gated clocking and delay lines

      "pseudo-SDF" generator efficiently solves race condition issues without the need to modify cell libraries

  • Detect simulation glitches using dynamic glitch detectors to uncover hard-to-find X corruption cases (0/X/1)

  • Uncover testbench forcing and connectivity issues in GLS

    • Force/release propagation analysis confirms when forces have been optimized away and no longer drive any fanout logic

      Connectivity analysis finds modules with undriven inputs that are creating X sources

  • Supports low-power-aware simulation

  • ECO flow improves turn-around time by re-verifying fixes from prior SimXACT runs after small netlist changes

  • Use plug’n’play setup

  • Supports Cadence Xcelium/IES, VCS, and Questa

  • Effectively root-cause the source of real X's with X Trace Viewer

    • Facilitates finding the root causes of real Xs that cause designs to operate non-deterministically when coming out of reset or during normal operation modes

      Supports one-step, automatic sequential back-tracing through hierarchical, mixed gate-level, RTL, and behavioral designs to show full X propagation history times over multiple clock cycles

      Integrates with Verdi, SimVision, and Questa to automatically scope Xs in source code and waveform views for full X propagation references

      Supports interactive, command line, and batch modes

      Uses structural RTL and formal-augmented X gate-level backtracing to identify real “controlling” functional support only, keeping X clutter down

      Provides FF corruption report for identifying X candidates that require analysis

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