Get onboard with Avery for the best in Verification IPs Automatic property synthesis enhances bug hunting and identifies testbench coverage holes X-Verification finds and eliminates X bugs in RTL and gate-level designs |
Early RTL Formal Analysis
Microarchitecture-level assertion and coverage synthesis and X-verification, low power verification. These solutions lead to improving the quality of your RTL design and verification, eliminate costly iterations, and improve overall schedule reliability. |
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Microarchitecture Property Synthesis Automates Assertion and Coverage Based Verification
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| SimXACT Delivers Precise Gate-level Simulation Accuracy When Unknowns Exist |
EDSFair2011 Seminar: New Developments in Early RTL Formal Analysis (English, Japanese) |
Robust Verification IP models and testsuites Avery is one of the leading and trusted suppliers of VIP to the chip and IP design community. |
PCI Express 1.1, 2.1, and 3.0
USB 2.0/OTG, 3.0, xHCI, and UAS
DDR3, DDR4, LPDDR2, LPDDR3, DFI-PHY, RDIMM, UDIMM, SO-DIMM
AMBA AHB, AXI3/4, and ACE
MIPI UniPro, M-PHY, UFS
NVM Express
SOP/PQI
SATA |
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Parallel Simulation Scales Performance by 5X or more
SimCluster parallel simulation delivers RTL and gate-level speed ups of 5X while using the simulators you already own including VCS, NC-Sim, or Questa |
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"Parallel Logic
Simulation: Myth or Reality?", IEEE Computer, April 2012
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