Avery Design Enhances Insight for Reachability Analysis, Lower Power Verification, and RT-Level DFT Analysis
ANDOVER, MA., June 8, 2010 – Avery Design Systems today announced its latest enhancements for Insight, the first behavioral-level, simulation-central formal analysis tool, now offering improved reachability analysis, low power verification, reset controllability analysis, and DFT analysis at the RT-level.
“Over the last year we have focused on increasing the breadth of solutions Insight formal analysis can offer designers as well as improving performance and capacity of traditional bug hunting and coverage test generation”, said Chilai Huang, president of Avery Design Systems.
Reachability analysis formally proves what RTL code and FSM state transitions are unreachable thereby helping to establish and justify coverage goals and simulation code coverage results. The latest enhancements now enable Insight to recognize more FSM modeling styles, perform deeper sequential enumeration using automatic guided search algorithms, and diagnose unreachable code and FSM transitions as either RTL bugs, testbench limitations, or redundant deadcode. Assertion synthesis has also been added covering a wide range of checks which can be exported and used in chip-level logic simulation.
Low power verification finds X propagations caused by RTL problems in power transition sequences which can be missed by logic simulation due to X-pessimism and X-optimism issues. Insight supports power-aware symbolic analysis and the UPF 2.0 standard. Now power transition sequences can be analyzed for possible retention, isolation, and reset problems. Chip-level analysis is supported using a fully automated flow including auto-partitioning of the chip and replay of VCD files comprising the power transition sequence simulations which are then formally analyzed.
Reset controllability analysis addresses logic simulation problems created by aggressive post route physical synthesis optimizations of the reset logic. Reset controllability formally proves that a design can be properly reset even when logic simulation is not deterministic due to X-pessimism.
DFT at-speed testability analysis can now be started earlier in the design process by performing accurate analysis on the RTL. After initial at-speed path transition testability coverage is generated and untestable paths categorized, Insight provides suggestions on how to harden the design for improved testability.
Avery Design will be hosting demonstrations of Insight and its full line of products including Verification IP (VIP) and distributed parallel simulation in booth #1363 at the 47th annual Design Automation Conference taking place in the Anaheim Convention Center from June 13-18, 2010. To register for demonstration slots, please email email@example.com.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables verification teams to achieve dramatic functional verification productivity improvements using formal bug hunting and coverage closure to improve design integrity, apply verification reuse methods using PCI Express, USB, AMBA, and SATA verification IP including comprehensive compliance testsuites, and gain scalable performance and capacity for system and SOC verification with distributed parallel simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs and has established numerous Avery Design VIP partner program affiliations with GDA Technologies, Snowbush, Northwest Logic, CAST, and Analog Bits. More information about the company may be found at www.avery-design.com.
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Avery Design Systems