Products Main
PCI-Xactor Test Environment
Complete core-through-chip verification slution
- PCIe 1.1, 2.0, 3.0 (Gen3), SR-IOV, MR-IOV
- PIPE 2.0, 3.0
Comprehensive BFM support
- Root Complex, Endpoint, Switch, PHY
- Robust API supports complex testing requirements
- Powerful error injection and completion control using callback and built-in methods
Built-in packet and complex operational sequence classes and constraints
Comprehensive directed tests for RC, EP, SW, and PHY
Packet and symbol tracker monitor output improves debug.
Packet, operational sequence, and asertion coverage monitor. Supports Verilog, SystemVerilog including OVM and VMM, Vera, SystemC, C/C++, and VHDL
SystemVerilog constrained random verification stresses DUT by applying complex sequence combinations for
read/write, LTSSM transitions, L-ans D-state power transitions, ACK protocol, replay, flow control, and
baseline and AER error handling.Functional coverage tracks range of TLP/DLLP traffic and complex operational sequences.
Comprehensive assertions track PCI-SIG compliance checklist coverage. Reference model-based scoreboard using advanced DUT integration methodology verifies correct DUT vs shadow reference model behavior.
Integration with LeCroy protocol analyzer enables advanced debug of HW observed bugs in normal simulation
environment.
Models and test suites provided in SystemVerilog/Verilog source code.
 
USB-Xactor Test Environment
Your Solution to Sperrspeed USB 3.0 Compliance Validation
Complete solution for core through chip-level verification
Superspeed USB3.0 and 2.0 OTG
UTMI, PIPE
xHCI
Comprehensive model support – Host, Device, Hub, PHY
Comprehensive compliance testsuite for Protocol, Link, and Physical layer verification
Supports Verilog and SystemVerilog OVM/VMM environments
Delivered in SystemVerilog source code
MIPI-Xactor Test Environment
Your Solution to
MIPI Compliance Validation
Complete solution for UniPro/M-PHY and UFS core through chip-level
verification
Host, Device, M-PHY models
Compliance testsuite for Transport, Network, Link, Physical layer
verification of Host, Device, PHY
Comprehensive assertions track MIPI compliance coverage
Functional coverage tracks range of packet traffic, FSMs, and complex
operational sequences
Packet and symbol tracker monitor output improves debug
Supports Verilog and SystemVerilog OVM/VMM environments
Delivered in SystemVerilog source code
Proven with multiple IP vendors
DDR-Xactor Test Environment
Your Solution to
DFI and DDR Compliance Validation
SDRAM memory models for DDR 3/4 and LPDDR 2/3
Complete DFI-PHY compliance solution for DFI 2.1 and 3.0
Comprehensive assertions track DFI and DDR compliance coverage
Functional coverage tracks range of traffic, FSMs, and complex operational
sequences
Protocol analyzer monitors DFI and JEDEC transactions for improved debug
Supports Verilog and SystemVerilog UVM/OVM/VMM environments
Delivered in SystemVerilog source code
Proven with multiple IP vendors
SATA-Xactor Test Environment
Complete solution to verify SATA 1/2/3, ATA/ATAPI-8 components
Complete BFM support - Host and Device models
Transaction class includes comprehensive random constraint set
Functional coverage reports device and command utilization
Verilog and VMM/OVM
Over 500 protocol checkers
Full compliance test suites
Insight :Early RTL Formal Analysis
Improve quality and streamline functional verification and DFT flows
Microarchitecture-level assertion and coverage property synthesis
- Automatically enhance verification and coverage property synthesis
- Augument user written assertions and coverage to fill holes
- Improve verification closure
At-Speed DFT Analysis and Repair
- Analyze RTL blocks for DFT rule checks
- Uncover issues preventing robust at-speed testing
- Automatically repair RTL with minimal test logic overhead
- Generate path delay fault test coverage and list of untestables
- Improve DFT closure
X-Verification
- Analyze designs for non-deterministic operation due to X sources
- Effectively debug X pessimism issues in gate-level simulations
- Mitigate X issues faster and make designs more robust
Simulation-centric formal analysis engine
- Easier to use than traditional formal tools
- Uses testbench or VCD for stimulus
- Integrated logic and symbolic simulator
SimCluster - Parallel Simulation
Distributed parallel simulation speeds up system-level simulation by 500% - 1,500%.
Increase RTL and gate-level simulation performance and capacity by 5-15 X
Supports gate-level simulation with full SDF back-annotation
Integrated flow with popular ATPG tools for rapid validation of scan and BIST vectors
Supports popular computing solutions of 2 to 10s of computers
Alternative to hardware acceleration solutions
Advanced behavioral and gate-level auto-partitioning
Trade-off signal-level versus transaction-level accuracy for improved performance
Works with most Verilog and VHDL simulators
AMBA - AXI/AHB
‧ Supports master, slave, and interconnect topologies
‧ Supports all bus widths
‧ Supports AXI4, AXI4-Lite, AXI4 Stream Protocol, AXI3, and AHB2.0 standard
‧ Supports VMM and OVM
‧ Transaction class includes comprehensive constraint set for random verification methodologies
‧ Supports wide range of callbacks for convenient error injection and scoreboarding checks
‧ Supports bus monitor and transaction tracker file generation
‧Works directly with the ARM AMBA3 and 4 Protocol Checker releases for comprehensive assertion-based verification
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