Avery Design Systems Spins Up ATA Verification IP Family
ANDOVER, MA., June 10, 2005 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced SATA-Xactor verification solution supporting the ATA protocol suite including SATA I and II, ATA/ATAPI-6, and CE-ATA. SATA-Xactor is a complete verification solution consisting of Bus Function Models (BFM), protocol checkers, test suites and reference verification frameworks for the functional verification of any Parallel ATA (PATA) and Serial ATA (SATA) component. The SATA-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their ATA compliant devices. Verification frameworks form complete testbench environments for host and device controller-based designs. Verification engineers can rapidly incorporate their designs into reference frameworks and begin running comprehensive verification tests. The SATA-Xactor environment leverages the advanced verification techniques of Avery’s TestWizard product supporting complex data structures, transaction database, random generation, temporal property checking, and coverage analysis.
- Complete solution to verify SATA I and II, ATA/ATAPI-6, CE-ATA components.
- Supports active test generation and passive link monitoring.
- Supports many environments - Verilog, SystemVerilog, Specman, Vera, SystemC, C/C++, and VHDL.
- Verification frameworks include reference testbenches for host an device components and ATAport driver integration with DUT to ease environment setup and maximize compliance test utilization.
- Test suites cover over 10 different categories to verify all ATA commands, reset, power modes under normal and error conditions.
- Tests are self-checking, portable, and reusable through a scenario-based development methodology comprised of parameterized test segment and scenario libraries that is extensible to writing custom tests.
- Over 250 assertion checks verify compliance across ATA Command, Transport, Data Link, Physical layers and includes assertions coverage.
- Models and tests are provided as open Verilog HDL source code.
- Advanced debug features include ATA command analyzer and SATA link and physical layer tracking.
Key BFM Features
- Robust BFMs (PATA, SATA) support all host & device functions
- Supports SATA 1.5 Gbps and 3.0 Gbps interface speeds and serial, 10-bit symbol, and physical plant interconnect interfaces
- Supports ATA 40 and 80 conductor cabling
- Robust API supports ATA commands including DMA, packet, and queued commands
- DMA setup supports memory buffer/descriptor allocation, initialization, and read-verify operations
- Disk store back-end model using sparse sector-based implementation
- Back-door read/write to host memory and disk sectors
- Control device response behaviors including request completion times
- Inject errors and noise at various layers
- Supports power management including hot-plug
- Configuration parameters control default settings, bring-up modes
About Avery Design Systems
Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process.
Additional information about Avery Design Systems is available at http://www.avery-design.com.
For More Information Contact:
Avery Design Systems
INDUSTRY KEYWORD: SOFTWARE COMPUTERS HARDWARE
ELECTRONICS NETWORKING EDA
ELECTRONIC DESIGN AUTOMATION
SOURCE: Avery Design Systems, Inc.