What have you been doing to evolve your verification closure and DFT closure methodologies?…
Well you better hurry up since the challenges are only going to get bigger! |
Early RTL Formal Analysis
Insight features microarchitecture-level assertion and coverage synthesis, X-verification, low power verification, and RTL At-Speed DFT analysis and repair. These solutions all lead to improving the quality of your RTL design and verification, eliminate costly iterations, and improve overall schedule reliability. |
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Improving At-Speed DFT Covrage Using Early RTL Testability Analysis  |
Microarchitecture Property Synthesis Automates Assertion and Coverage Based Verification
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| Using Formal to Analyze Non-Determinism in Design Reset Schemes |
EDSFair2011 Seminar: New Developments in Early RTL Formal Analysis (English, Japanese) |
Robust Verification IP models and testsuites Avery is one of the leading and trusted suppliers of VIP to the chip and IP design community. |
PCI Express 1.1, 2.1, and 3.0 USB 2.0/OTG, 3.0, xHCI, and UAS SATA 1,2,3
AMBA AHB and AXI3/4 |
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Parallel Simulation Scales Performance by 5X or more
SimCluster parallel simulation delivers RTL and gate-level speed ups of 5X while using the simulators you already own including VCS, NC-Sim, or Questa |
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Application note: A guide tour of Simcluster |
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